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Makefile 'for' variable as dynamic variable name

问题描述:

I have some dynamically named variables in Makefile. That all works and is fine.

Now I need to reference some of those variables in a for loop, but I can't seem to find the right syntax:

@for module in $(MODULES); do \

(echo $(SRC_$$module)); \

done

each $(MODULE) is a name that needs to be appended to $(SRC_.. for example $(SRC_foo) $(SRC_bar)... but I can't seem to do that with this syntax.

网友答案:

You have expansion-time issues. You can't expand make-level variables dynamically once the shell has started to run. Which is what you are trying to do here.

You either expand the variables at make time or at shell time but not both.

To expand everything at make time you can use something like this.

@$(foreach module,$(MODULES),$(foreach cfile,$(SRC_$(module)),echo '[$(cfile)]';))

Expanding at shell time is possible but a bit messier/trickier.

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