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Pattern generation using Vhdl...?

问题描述:

I need to generate led pattern of 16 bits...my delay is not working to generate desired pattern.....

Also my for loop is not working properly with delay

just i need a help ow to genrate pattern using any no. of bit using delay...????

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counters_1 is

port(CLK : in std_logic;

Q : out std_logic_vector(2 downto 0);

led_out : out std_logic_vector(15 downto 0));

end counters_1;

architecture archi of counters_1 is

signal tmp: std_logic_vector(2 downto 0) := "000";

begin

process (CLK)

begin

-- variable i :Integer :=0;

-- variable j :Integer :=0;

if (CLK'event and CLK='1') then

tmp <= tmp + 1;

if( tmp="100") then

tmp <="000";

end if;

end if;

if(tmp="00") then

loop1: for i in 0 to 10 loop

led_out <="0000000000000001" ;

led_out <="0000000000000010" ;

end loop;

end if;

if(tmp="01") then

loop2: for i in 0 to 10 loop

led_out <="1111111100000000";

led_out <="000000001111111" after 500 ms;

end loop;

end if;

if(tmp="10") then

loop3: for i in 0 to 10 loop

led_out <="0011000000000101";

led_out <="0000000111000110" after 500 ms;

end loop;

end if;

if(tmp="11") then

loop4: for i in 0 to 10 loop

led_out <="0000001100000111" after 500 ms;

led_out <="0000000000001000" after 500 ms;

led_out <="0001001000001000" after 500 ms;

led_out <="0000000000001000" after 500 ms;

led_out <="0100001100000111" after 500 ms;

led_out <="0000000000001000" after 500 ms;

led_out <="0010001000001000" after 500 ms;

led_out <="1000000000001000" after 500 ms;

led_out <="0001001100000111" after 500 ms;

led_out <="0000000000001000" after 500 ms;

led_out <="0011001000001000" after 500 ms;

led_out <="0000000000001000" after 500 ms;

led_out <="0100111100000111" after 500 ms;

led_out <="0000011110001000" after 500 ms;

led_out <="0010001000001000" after 500 ms;

led_out <="1000001110001000" after 500 ms;

end loop;

end if;

end process;

Q <= tmp;

end archi;

网友答案:

In the event you are doing RTL design, you need to think about the hardware in your problem much more. Draw pictures. Code the pictures.

To help this process, you need to consider the following:

  • How fast is clock running?
  • How are you going to create a 500 ms indicator from your clock? (Hint: counter + decoder)
  • Switching tmp on Clk is too fast.
  • To get the sequence in loop4, you are going to need a statemachine or another counter and decoder

Ask more questions once you have thought about your problem more.

网友答案:

Your code looks like a testbench, so I am going to assume that is what you wanted. Your issue revolves around understanding "after". "After" is used to schedule a delay on a signal. However, it never stops the process. The signal value is scheduled and the process moves on without any time passing.

On the other hand, what you want to have happen is for the process to stop. You need to use wait to cause the process to stop.

Using this for your code in loop4:

 loop4: for i in 0 to 10 loop
   wait for 500 ms ;
   led_out <="0000001100000111" ;
   wait for 500 ms ;
   led_out <="0000000000001000" ;
   wait for 500 ms ;
   led_out <="0001001000001000" ;
   ... 

If this is a testbench, you will not need to run your process based on Clk, instead, these type of processes run based on "wait" waking up.

You also probably don't need tmp. If you do decide you need tmp, either make it only 2 bits (this is ok as the counter will roll over) or your comparisons need to be use a slice as shown below. In addition, read up on the differences between signal and variable update. For a testbench, you definitely want to use a variable here (in addition, your code is incorrect unless you make it a variable).

if(tmp(1 downto 0) ="00") then

I will create a separate post in the event you are doing RTL code.

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