systemverilog assertion环境实战指导

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最近复习了下systemverilog assertion,做了个小例子,就贴在这里吧。

这里以一个边沿检测器为例来说明。

边沿检测器代码:

//file name pos_det.sv

`timescale 1ns/1ps

module pos_det( input bit clk, input bit rst_n, input bit det_signal, output bit pos_det);

always @(posedge clk or negedge rst_n) begin if(!rst_n) begin det_signal_d1 <= 1'b0; end else begin det_signal_d1 <= det_signal; //non-block end endassign pos_det = det_signal && (~det_signal_d1);

endmodule

 

 //file name pos_det_tb.sv

//test fixturemodule TBplatform(); //data type (signal) declare bit clk; bit rst_n; bit det_signal; bit pos_det;

//DUT instanced pos_det pos_det_inst( .clk (clk), .rst_n (rst_n), .det_signal (det_signal), .pos_det (pos_det) );

//initial procedural block,apply stimulus initial begin rst_n = 0; det_signal = 1; #50ns; rst_n = 1; #20ns; det_signal = 0; #100ns; det_signal = 1; #50ns; det_signal = 0; #500ns; det_signal = 1; #200ns; det_signal = 0; #350ns; det_signal = 1; #600ns; det_signal = 0; #20ns; det_signal = 1; #20ns; det_signal = 0; #30ns; det_signal = 1; #50ns; det_signal = 1; #80ns; det_signal = 1; #950ns;

#1us; $display("\ntestbench is ended at %0t \n",$time); $finish(2);

end

endmodule

 

//file name assert_code.sv 

module assert_code( input bit clk, input bit rst_n, input bit det_signal, //caution :DUT output signal(pos_det)should be declared as//input in assertion codeinput bit pos_det

);

property p1; @(posedge clk) disable iff(!rst_n) det_signal |-> pos_det;endproperty

//below only check posedge det_signal//property p1;// @(posedge clk) disable iff(!rst_n)// $rose(det_signal) |-> (det_signal && pos_det);//endproperty

a1:assert property(p1) begin $display("\n assert meet at %0t\n",$time);end

endmodule

//caution :bind block should outside assertion module//keyword dut name assert name assert instance namebind pos_det assert_check assert_check_inst(.*);

 

建立一个filelist文件,将上面的三个文件include进来。

 

 

 

1,建立文件vcs_run_cmd,里面的内容如下:

设置vcs或者modelsim或者ncsim的路径

setenv FSDB_SVA_SUCCESS 1

setenv VERDI_HOME  /XXX/XXX/

setenv NOVAS_HOME   /XXX/XXX/

setenv VERDI_HOME  $NOVAS_HOME

vcs +v2k -v2005 -debug_access+all -lca -sverilog -f filelist -l vcs_comp.log

#below for command line run mode

simv -ucli -do wave.do+fsdbfile+TBplatform.fsdb

#below for gui run mode

./simv -gui

#below for open verdi

verdi -f filelist -sv -2005 +systemverilog &

#below for clean temporary files

rm -rf *.fsdb ucli.key vcs_comp.log vcs.log novas_dump.log simv simv.daidr DVEfiles csrc inter.vpd novas.rc novas.conf

 注:

1,开verdi的时候,如果不加后面的 -sv -2005 +systemverilog,则很多systemverilog的语法verdi是不认的,verdi默认是加载verilog的语法。

2,filelist里可以将设计代码文件和testbench代码文件全部包含进来。

 

2,wave.do里面的内容如下:

fsdbDumpvars 0 TBplatform

run100us

exit

 

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